National Chung Cheng University
Electrical Engineering · Graduated
Current interests center on analog integrated circuit design, supported by power-management and regulator project experience.
Resume
Engineering Resume
A concise view of education, selected IC design projects, verification scope, technical skills, and language proficiency.
Professional Summary
Electrical engineering graduate focused primarily on analog IC design, with power-management and regulator projects providing the core engineering evidence. Additional schematic and pre-layout simulation work extends into data-converter front ends and RF circuits. Engineering records distinguish nominal, PVT, Monte Carlo, and extracted post-layout evidence while retaining unmet specifications and verification boundaries.
Education
Selected Engineering Projects
Capacitorless Linear Regulator
Capacitorless Linear Regulator with Gain-Peaking Suppression and Transient-Response Enhancement
- Operating conditions
- 810
- Monte Carlo samples
- 1000
- Completed the literature review, circuit implementation, small-signal and PVT/Monte Carlo verification, and transient-accelerator design iterations.
- Selected worst-condition Monte Carlo：Executed
- Verification scope and limitation：Worst heavy-load phase margin was approximately 55°, below the original greater-than-60° target.
6-bit SAR ADC Analog Front End
6-bit SAR ADC Analog Front-End Design and Integration
- Resolution
- 6 bit
- Nominal conversion error
- −0.0469 LSB
- Designed and verified the CDAC and StrongARM comparator, integrated the floating-VTOP interface, and analyzed kickback- and mismatch-related decision failures.
- Integrated nominal：Executed
- Verification scope and limitation：The completed scope is the analog front end, not a complete closed-loop SAR ADC.
2.4 GHz Cascode LNA
2.4 GHz Cascode Common-Source LNA Design and Robustness Analysis
- PVT validation
- 45 cases
- Core RF metrics
- S12 / NF / P1dB
- Built the LNA architecture and RF testbenches, performed operating-point and matching design, and completed S-parameter, noise, linearity, stability, and PVT/Monte Carlo analyses.
- S12, NF, and P1dB：Robust pass · 45/45 each
- Verification scope and limitation：The current output network did not meet the intended output-matching target across the 45-case PVT sweep. The result localized the main issue to output-impedance transformation, which will be redesigned around the actual load in the next iteration.
8-bit DLDO Pre/Post-Layout
8-bit DLDO Design with Pre- and Post-Layout Simulation
- Verification level
- Pre / Post
- Physical-design result
- Layout
- Designed and integrated the comparator, saturating counter, and PMOS power array, completed layout for the reported blocks, and compared pre- and post-layout behavior.
- Pre- / post-layout simulation：Executed
- Verification scope and limitation：Process, clock frequency, load conditions, and some measurement definitions are incomplete.
Technical Skills
Circuit Design
Simulation and Verification
IC/EDA Design Tools
Programming
Language Proficiency
- TOEFL iBT
- 107
- TOEIC Listening & Reading
- 980