Capacitorless Linear Regulator with Gain-Peaking Suppression and Transient-Response Enhancement
Studied and implemented a capacitorless linear regulator using damping-factor control to suppress gain peaking, then added a transient-accelerator path to improve load-transient behavior. The project included small-signal analysis, bias and reference design, PVT-condition sweeps, and worst-condition Monte Carlo simulations.
Quick Summary
30-second project summary
- Project objective
- This project was based on a literature-proposed DFC architecture. I implemented and evaluated the circuit, performed small-signal and PVT/Monte Carlo verification, and added and iterated the transient-accelerator path.
- My contribution
- Completed the literature review, circuit implementation, small-signal and PVT/Monte Carlo verification, and transient-accelerator design iterations.
- Strongest verified result
- Load-transient overshoot · 189 mV → 126 mV
- Main limitation / redesign focus
- Worst heavy-load phase margin was approximately 55°, below the original greater-than-60° target.
- Verification level
- Schematic-level design and simulation study
Target Specifications and Final Results
Pass or fail is assigned only when the original report defined an acceptance threshold. Metrics without an original threshold are presented as reported results without post-hoc specifications.
Except for the phase-margin target of greater than 60°, the original report did not define numerical acceptance thresholds for most performance metrics. Only phase margin is evaluated against an explicit acceptance threshold; the remaining metrics are reported without post-hoc limits.
Design Baseline
- Process
- U18 0.18 µm CMOS
- Regulated output
- 1.0 V nominal; tolerance not originally defined
- Input-voltage range
- 1.2 to 1.8 V
- Temperature
- -40, 50, and 125 °C
- Load range
- 100 µA to 100 mA
- PVT sweep
- 810 conditions
- Monte Carlo
- 1000 runs with process and mismatch enabled at selected worst-case conditions
Target Specifications and Final Results
| Metric | Target | Result | Scope | Status | Note |
|---|---|---|---|---|---|
| Phase margin | > 60° | No-MC worst = 66.157° heavy / 66.305° light; MC worst ≈ 55° heavy / ≈ 64° light | 810-condition PVT + 1000-run MC | Partial | The non-MC and light-load MC results meet the target, but the worst heavy-load MC result falls below 60°. |
| Output-voltage range | 1.0 V nominal; tolerance not originally defined | Approximately 0.95 to 1.07 V under MC | 1000-run MC | Reported only | — |
| Loop gain | Not originally defined | MC worst ≈ 64 dB heavy / ≈ 60 dB light | 1000-run MC | Reported only | — |
| Gain-bandwidth product | Not originally defined | MC worst ≈ 0.8 MHz heavy / ≈ 0.9 MHz light | 1000-run MC | Reported only | — |
| Line regulation | Not originally defined | MC worst ≈ 0.4 mV/V | 1000-run MC | Reported only | — |
| Load regulation | Not originally defined | MC worst ≈ 8 mV/A | 1000-run MC | Reported only | — |
| Load-transient overshoot / undershoot | Not originally defined | MC worst ≈ 185 mV overshoot / ≈ 660 mV undershoot | 1000-run MC | Reported only | — |
| PSR @ 1 kHz | Not originally defined | MC worst ≈ -36.2 dB heavy / ≈ -35.8 dB light | 1000-run MC | Reported only | — |
| PSR @ 10 kHz | Not originally defined | MC worst ≈ -31.3 dB under both loads | 1000-run MC | Reported only | — |
| Reported total power | Not originally defined | MC worst ≈ 200 mW heavy / ≈ 1.7 mW light | 1000-run MC | Reported only | Presented as total power according to the original report and not reinterpreted as quiescent power. |
On this page
Visual overview
Key metrics
- Operating conditions
- 810
- Monte Carlo
- 1000
- Overshoot
- 189 → 126 mV
- Worst heavy-load PM
- ≈ 55°
non-Monte-Carlo
process-and-mismatch samples
without / with TA
Visual overview
Verification coverage
- ExecutedDFC gain-peaking suppression
- ExecutedTA overshoot improvement
- Executed810 operating conditions
- ExecutedSelected worst-condition Monte Carlo
- Future verificationFull layout and PEX
- Out of scope for this phaseSilicon measurement
Transient-accelerator comparison
Load-transient overshoot
Problem & Design Goal
This project was based on a literature-proposed DFC architecture. I implemented and evaluated the circuit, performed small-signal and PVT/Monte Carlo verification, and added and iterated the transient-accelerator path. The work focused on trade-offs among stability, transient response, power, and circuit complexity.
My Contribution
- Reviewed LDO compensation and gain-peaking literature
- Compared a conventional LDO with a DFC-based architecture
- Analyzed the error-amplifier output pole, output pole, complex poles, and damping factor
- Implemented and simulated DFC and gm-boosting paths
- Designed and evaluated constant-gm bias and bandgap-reference blocks
- Added and iterated a transient-accelerator path
- Compared circuits with and without DFC and with and without the transient accelerator
- Evaluated 810 non-Monte-Carlo operating conditions
- Ran 1000-sample process-and-mismatch Monte Carlo simulations at selected worst conditions
- Analyzed stability, loop gain, GBW, power, regulation, transient response, and PSR
- Studied layout matching, common-centroid placement, and physical-design principles
Architecture & Method
- Error Amplifier / Gain Stages
- Pass Device
- VOUT
- Feedback
- DFC path for damping control
- TA path for transient acceleration
- Bias / reference blocks
Design and verification method
The study first compared a conventional LDO with the literature-based DFC architecture and analyzed the error-amplifier output pole, output pole, complex poles, and damping factor. It then implemented the DFC, gm-boosting, constant-gm bias, and bandgap-reference paths. After the TA was added, AC and transient behavior were compared with and without DFC and with and without TA. The final study covered 810 non-Monte-Carlo operating conditions and 1000-sample process-and-mismatch Monte Carlo simulations at selected worst conditions.
The design phase-margin target was greater than 60°. That target is kept separate from the Monte Carlo observations below; neither one comparison case nor an approximate observation is treated as an all-condition signoff result.
This project re-implemented a published circuit architecture and completed device sizing, integration, and simulation-based verification. The figures below are author-generated simulation results; they do not imply that the published architecture was original to this project.
DFC stability and transient evidence
The AC comparison connects damping-factor control to the observed loop response, while the load step shows the practical difference between the compensated and uncompensated cases.
Light-load loop response
Load-transient comparison
Design Challenges & Engineering Decisions
Case 01
Light-Load Gain Peaking and Stability Degradation
- Challenge
Without DFC, pronounced gain peaking appeared under light load, with oscillation and poor phase margin in some load-transient conditions.
- Diagnosis
At light load, lower pass-transistor gm moves the associated complex-conjugate poles toward lower frequencies. The resulting low-damping gain peaking forms near crossover and compresses phase margin.
- Design Response
A damping-factor-control path was added. Its additional negative-gain path and compensation capacitor increase the damping of the complex-conjugate poles, with related device sizes adjusted from the small-signal analysis.
- Outcome
DFC substantially suppressed gain peaking and removed the oscillation previously observed in the selected light-load transition condition.
- Trade-off or Next Step
The observed worst heavy-load Monte Carlo phase margin remains approximately 55°, below the original greater-than-60° target. The result is therefore an improvement, not an all-condition pass or signoff.
Case 02
Transient Overshoot after Stability Improvement
- Challenge
After DFC improved stability, load-transient overshoot and undershoot still required further improvement.
- Diagnosis
The error amplifier has limited bandwidth and cannot charge or discharge the pass-MOS gate quickly enough during abrupt load changes, delaying the pass device conduction adjustment.
- Design Response
A Transient Accelerator was added. Dynamic biasing detects changes in an error-amplifier branch and provides an additional momentary gate charging or discharging path.
- Outcome
Load-transient overshoot decreased from approximately 189 mV to approximately 126 mV, while the undershoot improvement was more limited.
- Trade-off or Next Step
Part of the Transient Accelerator discharge path does not fully turn off in steady state, leaving non-ideal leakage current. The case remains improved rather than fully resolved.
Verification Results
DFC comparison
- Without DFC, the compared light-load case showed a phase margin of −36.52°
- The DFC architecture suppressed the gain-peaking behavior observed in the comparison circuit
- This was one comparison condition, not a result for every operating condition
Transient Accelerator
- Load-transient overshoot improved from 189 mV to 126 mV
- The improvement in undershoot was limited
- Test condition: All Typical Case, Vin = 1.2 V, Temp = 50 °C
Transient-accelerator trade-off
Paired output traces show a clear overshoot reduction, while the undershoot responses remain close under the reported condition.
Overshoot
Undershoot
Condition sweep and Monte Carlo
- 810 reported non-Monte-Carlo operating conditions
- 1000 Monte Carlo samples with process and mismatch enabled
- Worst non-Monte-Carlo conditions were used for capacitor, temperature, and supply selections
- Heavy-load phase-margin worst value: approximately 55°; light-load: approximately 64°
- Heavy-load loop-gain worst value: approximately 64 dB; light-load: approximately 60 dB
- Heavy-load GBW worst value: approximately 800 kHz; light-load: approximately 900 kHz
All Monte Carlo values above are approximate observations, not precise signoff numbers.
Selected robustness evidence
This selected heavy-load distribution documents the simulated phase-margin spread; it is evidence for the reported study, not an all-condition signoff claim.
Heavy-load phase margin
Bandgap-reference robustness
This result supplements the bias/reference implementation by showing the simulated reference spread under one selected high-supply worst-case condition; it is not an all-condition signoff result.
High-supply worst-case condition
Engineering Insights
- The original TA discharge path responded too slowly because of its multi-stage path
- Simplifying the discharge path reduced control gain and made full turn-off more difficult
- The transient accelerator improved overshoot substantially but had limited effect on undershoot
- DFC, gm boosting, and transient acceleration had to be considered together with stability, power, and area
Validation Boundary & Limitations
- The original phase-margin target was greater than 60°, but the reported worst heavy-load Monte Carlo result was approximately 55°
- The transient accelerator retained non-ideal steady-state current or leakage
- DFC, gm boosting, and transient acceleration increase circuit complexity, area, and power
- Full layout, PEX, and silicon measurement were not completed
- The results do not establish that every PVT or Monte Carlo sample met every specification
Next Focus
- Redesign the TA discharge path
- Reduce steady-state leakage
- Recover heavy-load phase-margin margin
- Co-optimize stability, transient response, power, and area
- Complete layout, extraction, and post-layout verification
Tools or workflow
- Synopsys HSPICE