2.4 GHz Cascode Common-Source LNA Design and Robustness Analysis

The first design produced approximately −9.79 dB S11 at 2.4 GHz and did not meet the strict input-match target.

The input-impedance real and imaginary terms depend jointly on gm/Cgs, source-degeneration inductor LS, gate inductor LG, and the resonance position. LG primarily adjusts the input reactance and resonance notch, while LS also affects the input real term, local feedback, gain, noise, and linearity.

Operating-point sizing and joint LG/LS tuning were used to reset the input match and resonance position.

Historical baseline nominal S11 improved from approximately −9.79 dB to approximately −25.08 dB. In the final PVT variant, relaxed S11 passed 45/45 and strict S11 passed 37/45.

Supplemental Monte Carlo retains a thin band-worst margin. Spiral Q, pad/ESD, routing parasitics, package effects, and PEX can shift resonance, so LG/LS must be retuned after layout. The best nominal value is not treated as a robust pass.

In the SS process corner, the initial LNA did not provide sufficient IIP3.

For this design at the observed SS-corner bias and RF swing, the original gate bias left insufficient overdrive and pushed the main RF transistor too far toward weak inversion. The resulting lower drain current, limited available gm and large-signal headroom, and greater sensitivity to device nonlinearity reduced IIP3. This observation is specific to this operating condition rather than a universal claim about weak inversion.

Gate-bias voltage VG was increased, raising transistor overdrive and moving the operating point toward a more suitable moderate or stronger inversion region.

SS-corner IIP3 improved. No undocumented before/after IIP3 value is inferred, and the final IIP3 remains preliminary, extraction-method sensitive, and dependent on the selected input-power range.

Higher VG also increases drain current, power, gm, and gain, adding pressure at fast/high-VDD corners. This SS-corner improvement therefore leads directly to the fixed-bias robustness issue in Case 4.

S22 remained substantially below target from the initial design through the final result: 0/45 PVT and 0/1000 in the metric-specific Monte Carlo study.

The resonant output tank converts drain current into RF voltage gain but does not implement impedance transformation from the high-impedance drain/tank node to a 50-ohm port. This is a systematic architecture issue rather than a process-corner or small-component-tuning problem.

The root cause is diagnosed, but a replacement output-matching architecture has not yet been implemented.

Gain, S12, and NF can remain strong while S22 is still the main formal blocker. A resonant load is not equivalent to a passed 50-ohm output match.

• For an external 50-ohm load, add an L-match, transformer, or buffer.
• For direct mixer-gate drive, co-design against the actual mixer input impedance.

Final strict S21 passed 27/45 and power passed 10/45. The main fast/cold/high-VDD issue was excessive gain, current, and power rather than insufficient gain.

VG had been increased to improve the SS-corner operating point and IIP3. With a fixed gate-bias voltage, transistor overdrive and drain current remain highly sensitive to process, temperature, and supply voltage. The same change that helped slow-corner IIP3 therefore increased fast-corner power and gain upper-limit failures.

Analysis shows that simply lowering VG again is not a complete solution because it can reintroduce SS/slow-corner limitations in gain, IIP3, NF, P1dB, and the input-match real term.

SS-corner IIP3, strict-S21 upper-limit failures, and power spread are now understood as coupled consequences of the bias operating point and PVT sensitivity. The next bias redesign has not been completed.

The next version should use a more stable current or bias reference instead of relying only on fixed VG, followed by joint tuning of:

• Device sizing
• Bias current
• LG/LS
• Output loading
• Linearity
• Gain upper limit
• Power budget