Mixed-SignalFeaturedProject completed

2026-07

6-bit SAR ADC Analog Front-End Design and Integration

Designed and integrated the analog front end of a 6-bit single-ended SAR ADC, including a binary-weighted charge-redistribution CDAC, a StrongARM dynamic comparator, and their floating-VTOP interface. The project focused on debugging comparator kickback and mismatch-related decision failures.

Date: 2026-07
Status: Project completed
Project domain: Mixed-Signal

Technologies

Verification stage and scope

Transistor-level
Schematic / pre-layout
Analog-front-end scope completed
Closed-loop ADC not completed

Quick Summary

30-second project summary

Project objective: Completed the CDAC, StrongARM comparator, and floating-VTOP analog-front-end integration for a 6-bit SAR ADC, with design iterations that reduced kickback.
My contribution: Designed and verified the CDAC and StrongARM comparator, integrated the floating-VTOP interface, and analyzed kickback- and mismatch-related decision failures.
Strongest verified result: Integrated kickback · ≈ 43–60 mV → ≈ 11.7–16.4 mV
Main limitation / redesign focus: The comparator retains an unresolved decision-rate limitation under process-and-mismatch Monte Carlo.
Verification level: Transistor-level

Target Specifications and Final Results

Pass or fail is assigned only when the original report defined an acceptance threshold. Metrics without an original threshold are presented as reported results without post-hoc specifications.

This project completed transistor-level nominal integration of a 6-bit CDAC and StrongARM comparator analog interface. Closed-loop SAR logic, a complete transfer curve, DNL/INL, dynamic performance, combined Monte Carlo, PVT, and PEX signoff have not yet been completed.

Design Baseline

Process: U18 0.18 µm CMOS
Simulator: HSPICE transient
VDD: 1.8 V
VCM: 0.9 V
VREFH / VREFL: 1.4 V / 0.4 V
Reference span: 1.0 V
Resolution: 6 bit
Ideal LSB: 15.625 mV
Final CDAC unit capacitor: 20 fF
Final CDAC total capacitance: 1.28 pF
Comparator: StrongARM dynamic comparator; DOUT = p
Target input: Vin = 1.0 V
Ideal final code: 100110₂ = 38₁₀

Target Specifications and Final Results

Metric	Target	Result	Scope	Status	Note
Comparator nominal sensitivity	Correct polarity at ±1 mV test inputs	Correct decisions at nominal and five process corners	Standalone comparator	Pass	—
Vin = 1.0 V manual SAR sequence	All bit decisions correct	All trial decisions passed	Integrated transistor-level transient	Pass	—
Final output code	100110₂	100110₂	Vin = 1.0 V manual sequence	Pass	—
Fixed-pattern input sweep	Comparator polarity follows the measured decision-margin sign	Correct polarity from Vin = 0.45 to 1.35 V	Fixed manual pattern	Pass	This is not a complete closed-loop Vin-to-code transfer curve.
Final VTOP error	No independent numerical threshold was originally defined	893.0169 mV versus 893.7500 mV theoretical; error = -0.7331 mV = -0.0469 LSB	Integrated nominal transient	Reported only	—
Comparator kickback	No independent numerical threshold was originally defined	Improved from approximately 43–60 mV to 11.7–16.4 mV	Integrated design iteration	Reported only	—
Comparator mismatch robustness	No formal yield threshold was originally defined	Approximately 84.8%–87.6% correct at ±8 mV over 1000 process + mismatch runs	Standalone comparator Monte Carlo	Preliminary	Mismatch-induced offset remains a major limitation, so robust yield cannot be claimed.
Closed-loop SAR transfer	Complete Vin-to-code conversion over the reference range	Not completed	Full ADC	Not verified	—
DNL / INL / missing codes	Requires a complete transfer curve; not completed in the current project	Not verified	Static linearity	Not verified	—
SNDR / ENOB / SFDR	Sampling frequency and input bandwidth have not been defined	Not verified	Dynamic performance	Not verified	—
Combined MC / PVT / PEX	Meet the same functional and performance criteria after combined variation and extraction	Not completed	Robustness and post-layout signoff	Not verified	—

Visual overview

Key metrics

Resolution: 6 bit
Ideal LSB: 15.625 mV
Final code at Vin = 1.0 V: 100110₂ = 38
Final VTOP: 893.0169 mV

Visual overview

Verification coverage

ExecutedStandalone CDAC
ExecutedComparator nominal / corner
ExecutedIntegrated nominal
ExecutedManual SAR sequence
Future verificationDigital closed loopClosed-loop SAR control and automated bit-by-bit conversion
Future verificationStatic linearityFull transfer curve, DNL/INL, and missing-code verification
Future verificationRobustness and dynamic performanceCombined Monte Carlo, PVT, and dynamic metrics
Future verificationPhysical verificationLayout and PEX

Kickback design iteration

Integrated kickback

Initial≈ 43–60 mV

Final≈ 11.7–16.4 mV

Problem & Design Goal

This project developed and integrated the analog front end of a 6-bit single-ended SAR ADC in stages. Its scope covered a binary-weighted charge-redistribution CDAC, a StrongARM dynamic comparator, and their floating-VTOP interface. Verification focused on nominal transistor-level integration, comparator kickback, and mismatch-related decision failures, not a complete closed-loop SAR ADC.

My Contribution

Built a 6-bit binary-weighted CDAC
Verified sampling, conversion, and charge redistribution
Constructed a manual SAR binary-search sequence
Ran capacitor-mismatch Monte Carlo analysis for the standalone CDAC
Designed a StrongARM dynamic comparator
Verified reset, evaluation, polarity, nominal sensitivity, and process corners
Ran process-and-mismatch Monte Carlo analysis for the comparator
Integrated the floating CDAC VTOP with the comparator input
Quantified and diagnosed comparator kickback in simulation
Iterated comparator sizing and CDAC unit capacitance
Compared theoretical decision margins with simulated VTOP values
Distinguished nominal, standalone, and combined robustness claims

Architecture

Simplified architecture: this diagram shows only the approved analog-front-end scope and is not a complete SAR ADC schematic.

Sampling Input
6-bit CDAC
Floating VTOP
StrongARM Comparator
p / q Decision

Design and verification method

The CDAC was first verified for sampling, conversion, and charge redistribution. The StrongARM comparator was separately checked for reset, evaluation, polarity, nominal sensitivity, process corners, and process-and-mismatch Monte Carlo behavior. The floating VTOP was then connected to the comparator input, kickback was quantified in simulation, and comparator sizing and CDAC unit capacitance were iterated.

The core design baseline was:

Resolution: 6 bit
Process: 0.18 µm CMOS
VDD: 1.8 V
VREFH / VREFL: 1.4 V / 0.4 V
Reference span: 1.0 V
VCM: 0.9 V
Ideal LSB: 15.625 mV
Final CDAC Cu: 20 fF
Final CDAC total capacitance: 1.28 pF
Comparator: StrongARM dynamic comparator

Design Challenges & Engineering Decisions

Case 01

Insufficient Decision Accuracy from Premature Regeneration

Improved

Challenge

The initial StrongARM comparator achieved only approximately 60% correct decisions in the relevant verification.

Diagnosis

Excessive tail current drove the comparator into latch regeneration before the input pair had enough time to establish the differential input current. With an underdeveloped initial differential signal, regeneration more readily amplified mismatch, noise, or internal-node asymmetry into an incorrect decision.

Design Response

The tail-current MOSFET was reduced in size. Lower evaluation current delayed the start of regeneration and gave the input pair more time to establish a differential signal consistent with the input polarity.

Outcome

The correct-decision rate and decision robustness improved in the tested condition. No undocumented final percentage or all-corner yield is inferred.

Trade-off or Next Step

Reducing tail-device size and evaluation current can increase regeneration delay and reduce comparison speed.

Decision time
Regeneration delay
Correctness
Setup margin

These quantities still require joint verification across PVT, mismatch, and the target clock period.

Case 02

Comparator Kickback Corrupting Small Decision Margins

Improved

Challenge: The standalone CDAC had the expected theoretical decision margins, but some trial bits were decided incorrectly after integration with the StrongARM comparator.
Diagnosis: Comparator evaluation disturbed the floating VTOP by approximately 43–60 mV. This exceeded both the approximately 25 mV b4 margin and the approximately 9.375 mV b1 margin, identifying analog-interface coupling rather than the SAR trial-code pattern as the main cause.
Design Response: Building on the comparator timing correction above, the integrated interface was iterated in stages:
Adjusted and reduced the comparator input and tail devices to lower switching-charge injection.
Increased the CDAC unit capacitor from 10 fF to 20 fF.
Increased Ctotal to 1.28 pF so the same kickback charge produces a smaller VTOP disturbance.
Outcome: Kickback decreased to approximately 11.7–16.4 mV. In the nominal Vin = 1.0 V manual sequence, all trial decisions passed and final error was approximately −0.0469 LSB.
Trade-off or Next Step: This supports nominal transistor-level integration improvement only. It does not establish combined Monte Carlo yield, a complete closed-loop SAR ADC, completed DNL/INL, complete ADC robustness, or tapeout readiness.

Case 03

Comparator Sizing Trade-off between Mismatch and Kickback

Diagnosed

Challenge

Standalone comparator design generally favors larger input-pair and latch-device area to reduce mismatch-induced offset, while the integrated interface favors a smaller comparator to reduce input loading, switching charge, kickback, and dynamic energy.

Diagnosis

A larger comparator can reduce mismatch and increase regeneration gm, but also increases input capacitance, kickback charge, and dynamic energy. A larger CDAC can reduce kickback voltage and capacitor mismatch, but increases area, reference-switching energy, sampling RC, and settling time.

Design Response

For nominal integration bring-up, the present compromise reduces the comparator input and tail devices while increasing CDAC Cu to 20 fF.

Outcome

Nominal integration improved, but comparator process-and-mismatch Monte Carlo still shows approximately 12–15% failure. Nominal or corner pass therefore does not imply yield pass.

Trade-off or Next Step

The next iteration must jointly examine:

Combined Monte Carlo
Decision-time sweep
Clock-period verification
CDAC settling sweep
Energy-per-conversion analysis

These studies are needed to balance comparator size, tail current, and CDAC size.

Transistor-Level Implementation

This project completed the transistor-level implementation and integration of the CDAC, dynamic comparator, and sampling network. The topology follows a conventional SAR ADC architecture; schematic implementation, device sizing, integration, and simulation-based verification were completed by the author.

Integrated, CDAC, and comparator schematics

The complete view documents the integrated analog-front-end signal path; the two local views preserve the binary-weighted CDAC branches and the comparator's regenerative and clocked-device detail at a more readable scale.

Complete SAR ADC analog-front-end schematic with the binary-weighted CDAC and sampling switch at left, the clocked dynamic comparator at center and upper right, and labeled VTOP, VCM, clock, and decision nodes. — Integrated transistor-level schematic of the CDAC, sampling path, and dynamic comparator.

Binary-weighted CDAC schematic with a VTOP bus, a sampling switch controlled by CLK_SAMP, a VCM connection, and capacitor branches from 10 to 320 femtofarads controlled by VBDUM and VB1 through VB6. — Transistor-level implementation of the binary-weighted CDAC and sampling switch used in the SAR ADC analog front end.

Dynamic comparator schematic showing the clocked precharge devices, cross-coupled regenerative nodes, input pair connected to VCM and VTOP, tail device, and p and q outputs. — Transistor-level implementation of the clocked dynamic comparator used in the SAR ADC analog front end.

Standalone mismatch and nominal integration

The standalone CDAC distribution establishes the mismatch study, while the integrated transient records the manual bit-by-bit conversion sequence at the nominal input case.

CDAC error Monte Carlo histogram in LSB units with a compact distribution centered near minus 0.16 LSB. — Standalone CDAC final-error distribution from the reported mismatch study.

Stacked transient traces of sampling control, comparator clock, stepped VTOP, common-mode reference, and complementary p and q decisions through a manual conversion sequence. — Nominal integrated transient for the manually sequenced 1.0 V conversion case.

Integrated Improvement & Verification

Vin = 1.0 V manual conversion — nominal integrated result

Ideal code: 100110₂ = 38
Final code: 100110₂
Final VTOP: 893.0169 mV
Theoretical VTOP: 893.7500 mV
Error: −0.7331 mV = −0.0469 LSB

Kickback reduction — design iteration

Initial integrated kickback: approximately 43–60 mV
Final integrated kickback: approximately 11.7–16.4 mV
The improvement came from reducing comparator input/tail sizing and increasing Cu from 10 fF to 20 fF

Standalone CDAC Monte Carlo

1000 runs
Final error mean: approximately −0.160 LSB
Standard deviation: approximately 0.012 LSB
The mismatch model was not based on final post-layout MIM-capacitor geometry and cannot be interpreted as DNL/INL yield

Remaining Robustness Issue

Nominal and five process corners could resolve ±1 mV
At ±8 mV under 1000-run process-and-mismatch Monte Carlo, the reported correct-decision rate was only approximately 84.8%–87.6%
This result is an unresolved mismatch limitation, not a successful yield metric

Failure discovery and unresolved comparator mismatch

The early integrated waveform records incorrect decisions during iteration; the final ±8 mV Monte Carlo view still contains wrong-polarity outcomes and therefore documents the remaining limitation.

Stacked clock, VTOP, common-mode, and comparator-output transients with long incorrect p and q decision states during the manual conversion sequence. — Early integrated transient used to identify decision failures during comparator and CDAC iteration.

Two side-by-side comparator-decision histograms dominated by the expected positive and negative output states but each retaining a smaller wrong-polarity group. — Process-and-mismatch Monte Carlo decision distributions at ±8 mV, including the remaining wrong-polarity outcomes.

These figures support root-cause analysis and improvement tracking; they do not establish combined analog-front-end yield.

Engineering Insights

An early netlist simulated only the comparator and did not actually include the CDAC
Integrated-v1 kickback exceeded the margins of small-decision bits
Reducing comparator size lowers kickback but can worsen mismatch-induced offset
Increasing CDAC capacitance reduces kickback and kT/C noise but increases area, settling time, and switching energy
Passing standalone blocks does not demonstrate integrated yield

Validation Boundary & Limitations

The completed scope is the analog front end, not a complete SAR ADC. The following work remains incomplete:

Closed-loop SAR control
Automated bit-by-bit conversion
Full input transfer curve
DNL and INL
Missing-code verification
Offset and gain-error extraction
Combined CDAC + switch + comparator Monte Carlo
Full PVT robustness
Sampling-frequency definition
FFT, SNR, SNDR, SFDR, THD, and ENOB
Layout and PEX
Silicon measurement

Accordingly, the page does not claim that closed-loop conversion, DNL/INL, ENOB, Monte Carlo yield, or post-layout verification passed.

Next Focus

Build closed-loop SAR control and automated bit-by-bit conversion
Complete full-input transfer, DNL/INL, missing-code, offset, and gain-error verification
Run combined Monte Carlo and full PVT robustness analysis
Define sampling frequency and evaluate FFT, SNR, SNDR, SFDR, THD, and ENOB
Complete layout, PEX, and silicon measurement

Tools or workflow

Synopsys HSPICE