Tsu-Ming ChangPersonal portfolio

IC Design Graduate Applicant Portfolio

Tsu-Ming Chang

Electrical Engineering | Analog IC Design

Focused primarily on analog IC design, with power-management and regulator projects forming the core evidence and additional experience extending into data converters and developing RFIC capability.

National Chung Cheng University · Electrical EngineeringNew Taipei City, Taiwan
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Selected engineering evidenceFrom circuit behavior to physical implementation

Engineering focus

Analog IC focus and extensions

Analog IC and power management form the main engineering foundation, with current projects extending into data converters and RF circuits. Counts show portfolio coverage, not proficiency.

Power Management

2

Analog LDO and digitally controlled DLDO work examining stability, transient response, and post-layout parasitic effects.

Capacitorless Linear Regulator with Gain-Peaking Suppression and Transient-Response EnhancementView project

Mixed-Signal

1

CDAC, dynamic-comparator, and analog-front-end integration with standalone and integrated evidence kept distinct.

6-bit SAR ADC Analog Front-End Design and IntegrationView project

RFIC

1

A 2.4 GHz LNA project used to build experience in RF testbenches, matching, S-parameters, and robustness analysis.

2.4 GHz Cascode Common-Source LNA Design and Robustness AnalysisView project

Selected work

Featured projects

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Output and load transient plots comparing the compensated DFC response with the oscillatory uncompensated response.
Load-transient comparison with and without DFC.
Power / RegulatorProject completed

Capacitorless Linear Regulator

This project was based on a literature-proposed DFC architecture. I implemented and evaluated the circuit, performed small-signal and PVT/Monte Carlo verification, and added and iterated the transient-accelerator path.

Operating conditions
810
Monte Carlo samples
1000
  • Analog LDO
  • Capacitorless Regulator
  • Damping Factor Control
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Integrated transistor-level SAR ADC analog-front-end schematic containing the CDAC, sampling path, and dynamic comparator.
Integrated transistor-level analog-front-end implementation.
Mixed-SignalProject completed

6-bit SAR ADC Analog Front End

Completed the CDAC, StrongARM comparator, and floating-VTOP analog-front-end integration for a 6-bit SAR ADC, with design iterations that reduced kickback.

Resolution
6 bit
Nominal conversion error
−0.0469 LSB
  • SAR ADC
  • CDAC
  • StrongARM Comparator
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Simulated 2.4 GHz noise-figure Monte Carlo histogram with most samples grouped near one decibel.
Selected-condition simulated noise-figure distribution at 2.4 GHz.
RFICProject completed

2.4 GHz Cascode LNA

Completed the schematic and pre-layout design of a 2.4 GHz inductively degenerated cascode common-source LNA in 180 nm CMOS. Across the 45-case PVT sweep, S12, noise figure, and input P1dB met their project targets in all cases, while output matching and bias/power robustness were identified as the main directions for the next design iteration.

PVT validation
45 cases
Core RF metrics
S12 / NF / P1dB

45/45

  • RFIC
  • LNA
  • S-Parameters
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Contact

Discuss graduate study and IC design

For questions about project scope, verification methods, or my current study direction, please get in touch by email.

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