Power / RegulatorProject completed

8-bit DLDO Design with Pre- and Post-Layout Simulation

Designed and integrated a DLDO architecture consisting of a latch comparator, an 8-bit saturating up/down counter, a binary-sized PMOS array, and an output-feedback path. Pre- and post-layout simulations were compared to examine the effects of parasitic RC, clock skew, and layout asymmetry.

Status: Project completed
Project domain: Power / Regulator

Technologies

Verification stage and scope

Pre-layout and extracted post-layout simulation
Layout completed for reported blocks
No documented DRC, LVS, or full PEX signoff

Quick Summary

30-second project summary

Project objective: Completed a DLDO integrating a latch comparator, an 8-bit saturating UP/DOWN counter, a binary-sized PMOS array, and feedback, with pre- and post-layout behavior compared.
My contribution: Designed and integrated the comparator, saturating counter, and PMOS power array, completed layout for the reported blocks, and compared pre- and post-layout behavior.
Strongest verified result: Pre- / post-layout simulation · Executed
Main limitation / redesign focus: DRC, LVS, and full PEX signoff are not documented, and no silicon measurement was performed.
Verification level: Pre-layout and extracted post-layout simulation

Target Specifications and Final Results

Pass or fail is assigned only when the original report defined an acceptance threshold. Metrics without an original threshold are presented as reported results without post-hoc specifications.

The original report provides Presim and Postsim results but does not define complete numerical acceptance thresholds, units for several metrics, full input/load-step conditions, or the clock frequency. This table therefore presents a Presim-to-Postsim comparison without assigning pass or fail.

Design Baseline

Architecture: Latch comparator → 8-bit up/down counter → binary PMOS switch array → load
Reference voltage: VREF = 0.85 V
Control resolution: 8-bit up/down counter
Power stage: Binary-sized PMOS array
Reported layout dimensions: 26.025 × 25.345 = 659.6The original report does not state the dimension or area units; µm or µm² must not be added.
Verification scope: Presim and Postsim comparison

Target Specifications and Final Results

Metric	Target	Presim	Postsim	Status	Note
Line settling time (rise)	Not originally defined	4.74 µs	11.5 µs	Reported only	—
Line settling time (fall)	Not originally defined	4.85 µs	11.3 µs	Reported only	—
Line undershoot	Not originally defined	65.21 mV	73.08 mV	Reported only	—
Line overshoot	Not originally defined	80.42 mV	86.03 mV	Reported only	—
Line regulation	Not originally defined	0.002106	-0.006401	Reported only	The original report does not state the unit or calculation definition.
Load settling time (rise)	Not originally defined	12.7 µs	24.8 µs	Reported only	—
Load settling time (fall)	Not originally defined	11.6 µs	23.6 µs	Reported only	—
Load undershoot	Not originally defined	397.6 mV	402 mV	Reported only	—
Load overshoot	Not originally defined	139 mV	140 mV	Reported only	—
Load regulation	Not originally defined	-0.4411	0.2143	Reported only	The original report does not state the unit or calculation definition, so this value must not be interpreted as a percentage, V/A, or another unit.
Output ripple	Not originally defined	34.3 mV	35.3 mV	Reported only	—
Quiescent current	Not originally defined	2.256 µA	4.152 µA	Reported only	—

Visual overview

Key metrics

Line-settling rise: 4.74 → 11.5 µs
Line-settling fall: 4.85 → 11.3 µs
Load-settling rise: 12.7 → 24.8 µs
Load-settling fall: 11.6 → 23.6 µs

Visual overview

Verification coverage

ExecutedSchematic design
ExecutedLayout for reported blocks
ExecutedPre- / post-layout simulation
Future verificationDRC / LVS / full PEX signoff
Out of scope for this phaseSilicon validation

Pre-layout versus post-layout

Line-settling rise

Pre-layout4.74 µs

Post-layout11.5 µs

Line-settling fall

Pre-layout4.85 µs

Post-layout11.3 µs

Load-settling rise

Pre-layout12.7 µs

Post-layout24.8 µs

Load-settling fall

Pre-layout11.6 µs

Post-layout23.6 µs

Output ripple

Pre-layout34.3 mV

Post-layout35.3 mV

Quiescent current

Pre-layout2.256 µA

Post-layout4.152 µA

Problem & Design Goal

This project designed and integrated a DLDO consisting of a latch comparator, an 8-bit saturating up/down counter, a binary-sized PMOS array, and an output-feedback path.

My Contribution

Designed the latch comparator and output-hold logic
Designed an 8-bit up/down counter
Added upper- and lower-bound saturation protection at codes 255 and 0
Designed a binary-sized PMOS power array
Integrated the comparator, counter, power stage, and feedback path
Produced layouts for the reported circuit blocks
Compared pre-layout and post-layout simulations
Debugged clock skew, routing RC, drive strength, and comparator asymmetry

Architecture & Method

Simplified architecture: this diagram presents the high-level feedback path documented in the report and is not a complete schematic.

Latch Comparator
8-bit Saturating UP/DOWN Counter
Binary PMOS Array
VOUT and Load
Feedback

The comparator reference is approximately 0.85 V. The counter output controls eight binary-weighted PMOS branches with approximately 1× to 128× relative drive capability. The saturation guard prevents count wraparound at 00000000 and 11111111.

Design and verification method

After integrating the comparator, 8-bit saturating counter, PMOS power array, and feedback path, presimulation and postsimulation were compared. The study examined how parasitic RC, clock skew, drive strength, and layout asymmetry affected settling, ripple, quiescent current, and transient excursions.

The current project records do not fully define the process, clock frequency, load conditions, or all measurement units. The figures below are therefore presented as pre-layout/post-layout comparisons, not as a complete specification signoff.

Layout Implementation

Physical layout was completed for the integrated circuit and the segmented PMOS power array. The available evidence supports completion of these reported layouts and evaluation through extracted post-layout simulation; it does not establish DRC, LVS, full PEX signoff, tapeout, or silicon measurement.

Physical implementation evidence

The overall view shows the integrated routing context; the second view exposes the repeated segmented power-device structure.

Complete DLDO physical layout with repeated control rows on the left, the routed PMOS power stage at upper right, and a long vertical power connection. — Top-level DLDO layout integrating the digital control, comparator, and PMOS power array.

Wide segmented PMOS power-array layout with repeated device fingers arranged in horizontal rows, shared rails, and vertical interconnect trunks. — Physical layout of the segmented PMOS power array used for digitally controlled output current.

Physical layout was completed and evaluated through extracted post-layout simulation. The waveform comparisons below provide the simulation evidence while preserving the documented verification boundary.

Verification Results

Pre-layout / post-layout comparison

Line-settling rise: presim 4.74 µs; postsim 11.5 µs
Line-settling fall: presim 4.85 µs; postsim 11.3 µs
Load-settling rise: presim 12.7 µs; postsim 24.8 µs
Load-settling fall: presim 11.6 µs; postsim 23.6 µs
Output ripple: presim 34.3 mV; postsim 35.3 mV
Quiescent current: presim 2.256 µA; postsim 4.152 µA

Line-transient comparison

Compare output recovery after the input-voltage transitions and observe the effect of extracted parasitics on settling time.

Red VOUT trace with positive and negative excursions after two input-voltage transitions and settling markers at 4.74 and 4.85 microseconds. — Pre-layout line-transient response under the specified input-voltage transition.

Red VOUT trace showing startup and two input-voltage transition responses with settling markers at 11.5 and 11.3 microseconds. — Post-layout line-transient response including extracted parasitic effects.

The marked settling intervals show that output recovery takes longer after extracted parasitic effects are included.

Load-transient comparison

Compare the output excursion and recovery under the specified load-current transition.

Red VOUT trace with undershoot and overshoot at the load transitions, settling markers at 11.6 and 12.7 microseconds, and steady-state ripple in the load states. — Pre-layout output response under the specified load-current transition.

Red VOUT trace with larger undershoot and overshoot at the load transitions, settling markers at 23.6 and 24.8 microseconds, and steady-state ripple in the load states. — Post-layout load-transient response after parasitic extraction.

The post-layout result shows longer settling intervals and more pronounced transient excursions, illustrating the impact of extracted parasitics on the load-step response.

Output-ripple comparison

Compare steady-state output variation before layout and after extracted parasitic effects are included.

Red VOUT trace with periodic triangular steady-state ripple and measurement markers showing approximately 34.3 millivolts peak to peak. — Simulated pre-layout steady-state output ripple.

Red VOUT trace with periodic triangular steady-state ripple and measurement markers showing approximately 35.3 millivolts peak to peak. — Simulated post-layout output ripple including extracted parasitics.

Both results retain a similar periodic trend; the recorded peak-to-peak ripple changes from 34.3 mV pre-layout to 35.3 mV post-layout.

Post-layout transient excursions

Line undershoot: 73.08 mV
Line overshoot: 86.03 mV
Load undershoot: 402 mV
Load overshoot: 140 mV

Engineering Insights

Post-layout parasitic delay substantially increased settling time
Long routing can introduce clock skew and counter glitches
Comparator layout asymmetry can cause logic errors
Digital correctness alone is insufficient when drive strength, setup/hold timing, and interconnect delay are considered
Post-layout verification exposed issues not visible in presimulation

Validation Boundary & Limitations

Process, clock frequency, load conditions, and all measurement units are not yet fully documented
DRC, LVS, and full PEX signoff are not documented
No silicon measurement was performed
Line regulation, load regulation, and schematic area are not published as formal specifications because their units and test conditions are insufficiently defined

Next Focus

Record the process, clock frequency, load conditions, and measurement definitions explicitly
Further verify long-routing effects, clock skew, counter glitches, and comparator asymmetry
Co-design physical layout and timing behavior in the mixed-signal control loop
Document DRC, LVS, and PEX status only when complete evidence is available

Tools or workflow

Schematic design
IC layout
Pre-layout simulation
Post-layout simulation